In order to avoid thin gate oxide damage to integrated circuits as a result of electrostatic discharge (ESD), special ESD protection circuits have been developed to shunt high ESD current pulses to ground. These, however, invariably take up a considerable amount of extra space on an integrated circuit to chip. It is therefore desirable to keep the number of such shunt circuits or clamps to a minimum. However, especially in the case of digital circuits, it is common to find extremely complex circuits with numerous inputs and outputs. Each of these pads presents a potential source for damage to the circuit and therefore needs to be coupled to an ESD clamp. As a space saving measure, instead of providing a separate clamp for each I/O pad, the I/O pads are, instead, coupled by means of diodes to the power rails, which, in turn, are provided with protective clamps. In this way, numerous inputs and outputs can be protected by a single ESD clamp. In a typical circuit, low resistive power supply rails (VDD, VSS) or separate rail buses are provided, and each I/O pin or pad is connected to these rails using p-well and n-well diodes as shown in the prior art circuit of FIG. 1. FIG. 1 shows a pad 10 connected by means of a p-well diode 12 to a VDD bus and by means of a n-well diode 14 to a VSS bus. The protected circuit, which in this case takes the form of an inverter 16, is protected by an ESD clamp 18 connected between the VDD and VSS buses. In the absence of the diodes 12, 14, the ESD clamp 18 would only protect the circuit 16 against ESD pulses on the power rails VDD or VSS. However, an ESD pulse on the pad 10 would be fed directly to the circuit 16, exposing the circuit to thin oxide damage. Through the addition of the diodes 12, 14 a positive ESD pulse to the pad 10 is channeled via the diode 12 through the ESD clamp 18. Similarly, a negative ESD pulse to the pad 10 is channeled through the ESD clamp 18 and the diode 14 to effectively protect the circuit 16 against all ESD current pulses. A typical p-well diode is illustrated in FIG. 2 and includes a p-well 20 formed in a p-substrate 22. A n+ region 24 and a p+ region 26 are formed in the p-well 20 and are separated by a shallow trench isolation region 27. FIG. 2 also shows the cathode contact 28 connected to the n+ region 24 and the anode contact 29 connected to the p+ region 26. FIG. 3, in turn, shows the structure of a n-well diode which comprises a n-well 30 formed in a p-substrate 32, with a p+ region 34 and a n+ region 36 formed in the n-well 30 and separated by a shallow trench isolation region 37. A cathode contact 38 is provided for the n+ region 36, and an anode contact 39 is provided for the p+region 34.
According to TLP measurements, the diode characteristics provide for reliable ESD operation during ESD current pulses of 4-6 V. This is also referred to as the VT2 value which is associated with a corresponding IT2 increase. However, when a diode operates in this dynamic range of power operation, it creates a danger of thin oxide damage to the internal I/O driver (such as the inverter in FIG. 1) and can occur even before the diode reaches its IVT2 burn out point. This problem is already starting to become apparent with current 0.18 mm/3.3V technology, but will become even more so in future as gate dimensions continue to be reduced and the operating voltage and corresponding gate oxide thickness and resultant breakdown voltage become ever smaller.
The problem is further exacerbated by the fact that the circuit interconnects provide a voltage drop which, for a 1 Ohm resistance provides for an extra 1 V drop for each Amp of current in the current pulse. While the diode effectively sees a lower voltage due to the voltage drop across the interconnect, the full voltage appears across the internal circuit being protected, namely the I/O driver. Referring to FIG. 1, the interconnects 13, 15 present the diodes 12, 14 with a lower voltage due to the voltage drop across the interconnects 13, 15. On the other hand, the internal circuit 16, which is connected in parallel and has its input connected to an external node 19, experiences the full ESD voltage seen by the diode 12 or 14, is well as the additional voltage drop across the interconnect 13 or 15.
A further factor to be considered is the internal capacitance of the ESD circuits when operating at high frequencies in the RF range. Also, limitations are placed on the choice of power diodes for the diodes themselves since the diodes have to be created using existing process technology, meaning that only junctions and regions from supported devices of existing technology are typically used to create the power diodes.
The present invention seeks to address the issue of providing a more efficient diode solution that takes into account the voltage limitations of the internal circuit to be protected, the need to keep the sizes of such diodes to a minimum, and preferably provide a solution that makes use of supported devices and avoids substantial new process steps.